1. Field of the Invention
The present invention relates to a signal processing apparatus for performing a coding/decoding and other processes on digital PCM signals, for example, by combining PCM.CODEC and a DSP (Digital Signal Processor), and more particularly, to a technology for realizing a practical signal processing in DSP by using equivalently high precision and inexpensive A/D or D/A converters, and to an output signal clock changing apparatus necessary for performing the above signal processing in synchronization with the same clock.
2. Description of the Related Art
The signal processing apparatus performs coding/decoding and other processes, for example, on digital PCM signals.
There are representative apparatuses, an A/D converter for performing a coding between an analog telephone band signal on a subscriber line and a digital PCM signal on a relaying line, and a D/A converter for performing a decoding therebetween.
Generally speaking, when an analog signal is converted to a digital signal on a receiving side, it is first sampled at predetermined intervals by using respective sampling signals, and then quantized with regard to respective sampling signals. Quantizing is executed to predivide the amplitude level of the analog signal into a plurality of ranges so that the analog signals within certain ranges can be represented by a corresponding representative digital value. The resulting quantized signal is transmitted on a transmission line as a digital PCM signal coded. On the receiving side, the digital PCM signal is reconverted to an analog signal and reproduced as a telephone signal such as a human voice.
During the quantizing process, a certain range of analog signals can be expressed by the same code, even if sampled values vary to some extent, and on the receiving side the sampled value within the range can be decoded as an analog signal of the same amplitude. Therefore, there may be a substantial difference, between an analog signal before coding and an analog signal after decoding. This difference is called quantization noise.
The signal to quantizing noise ratio (S/N) is used to evaluate the quality of the communicated signal. The range presented by one code is called a quantizing step. When the quantizing step is uniform, quantizing noise is constant. Therefore, if the signal, namely, the amplitude of the analog input is large, S/N is high. If it is small, S/N is low. However, for good communication quality, S/N should be maintained constant regardless of the above amplitude. A nonlinear quantization in which the quantizing step is made small for an analog input with a small amplitude, and large for an analog input with a large amplitude, is generally adopted. This is called companding. To produce good companding characteristics for a nonlinear quantization of a telephone signal, a companding rule called .mu.-law is adopted in Japan and the United States, and a companding rule called A-law is adopted in other areas, including Europe and parts of Asia.
Recently, 8 bit companding A/D or D/A converters for performing a signal conversion based on the above companding rule have been produced by many makers. Although their structures are complicated, they are relatively inexpensive. The ICs are generally called "PCM.CODEC." (PCM coder/decoder).
On the other hand, when data transmission other than voice signals is conducted by using a telephone band signal, a signal processing circuit such as an equalizer, an attenuator or a balancing network is redundant when combined with a converter such as a PCM.CODEC. These circuits are conventionally constructed as analog circuits. On a coding side they are provided in a stage before an A/D converter, and on a decoding side in a stage after a D/A converter.
FIG. 1 shows a conventional digital PCM channel apparatus which can be realized as a combination of the above circuits and a PCM.CODEC.
PCM.CODEC 1 comprises an A/D converting unit including a low-pass filter (LPF) 7 and an A/D converter 8, and a D/A converting unit including a D/A converter 10 and a LPF 11. A/D converter 8 and D/A converter 10 conduct data conversion based on 8-bit .mu.-law companding. LPFs 7 and 11 limit the frequency range of the analog signals which are respective input/output signals, to a frequency band which can be expressed by a sampling frequency, namely they are law pass filters for limiting a frequency band up to 1/2 the sampling frequency. As described above, PCM.CODEC 1 integrally forms a low-pass filter in a chip. As a result the cost of coding/decoding portions can be reduced.
Hybrid transformer 3 divides an analog telephone band signal (analog data) transmitted on a 2-wire subscriber line 2 into a transmitting signal and a receiving signal. Equalizers 4 and 13 correct the loss of frequency characteristics of signals in 2-wire subscriber line 2 or 4-wire transmission path 9 within a telephone band. Attenuaters 6 and 12 correct the signal level loss caused during propagation along a line. Balancing network 15 adjusts the impedance of hybrid transformer 3 in order to reduce leak (echo-back) of signals from the receiving side to the transmitting side, the leak being caused by an impedance mismatching in hybrid transformer 3. Amplifiers 5 and 14 adjust the signal levels. Setting and controlling of the above circuits is conducted electrically by a remote control of a center (station) not shown, as designated by the dotted line in FIG. 1. This control is generally called a remote provision.
The above circuits 4,6,12,13 and 15 are important circuits which are necessary for increasing the communication quality. However, when they are analog circuits, they are large and the cost of the apparatus as a whole becomes high. Provision for remotely setting a plurality of analog circuits becomes complicated.
However, DSPs (Digital Signal Processor) have started to become widely used in various fields, and LSIs of DSPs can be obtained at a low price. The performance of DSPs has increased annually, and a circuit portion subjected to a conventional analog process is replaced by a DSP process. This is also because the scale of the hardware can be reduced by a DSP process. Use of a DSP suppresses the effect of deviations caused among various kinds of products and in the manufacturing process, to a minimum value, although the deviations in the manufacturing process have a large effect on products in an analog circuit. Further, only a modification of installed firmware can facilitate a change in a process operation. Based on this technology, units conventionally subjected to an analog process are replaced by a DSP in the field of telephone band signal processing. It is desired that the aforementioned equalizer, attenuator, and balancing network be replaced by a DSP.
FIG. 2 shows the structure of a digital PCM channel apparatus, in which the process of the above respective circuit is conducted by a DSP. In FIG. 2, portions designated by the same reference numbers as in FIG. 1 perform the same function as the portions in FIG. 1. As shown in FIG. 2, DSP 16 is provided on the digital signal side of PCM.CODEC 1, and the same function as the impedance control of hybrid transformer 3, which is conducted in balancing network 15 in FIG. 1, can be realized by DSP16. Therefore, the impedance of hybrid transformer 3 is fixed at a constant value as is conceptually represented by resistance value R in FIG. 2 and an occurrence of signal leakage is allowed. Coarse attenuators 17 and 18 perform a rough adjustment of signal level in the 3 dB range of analog signal, and also have a preprocessing function.
As shown in FIG. 2, DSP 16 is preferably combined with PCM.CODEC1 which is available at a low cost. However, mere combination of DSP16 and PCM.CODEC 1 cannot realize a coder and decoder apparatus with a desired performance. This is because of the recited S/N ratio. According to a .mu.-law companding by PCM.CODEC, a digital signal coded on a transmitting side is transmitted to a receiving side through a transmission path without suffering any modification, and is decoded on the receiving side following the same companding rule as on the transmitting side and the .mu.-law companding is a kind of code conversion rule determined based on the above condition. Therefore, when DSP processing is applied to a digital signal after an A/D conversion, a quantizing noise instinctively occurring only upon coding is also produced upon decoding. Thus, in order to raise the communication quality the number of quantizing bits must be made as large as possible, and the respective quantizing steps made as small as possible, thereby suppressing quantizing noise to a minimum value. Most currently available PCM.CODECs perform an eight bit quantization, and the accuracy of this quantization is relatively low. Therefore, there is a problem that deterioration of communication signal S/N cannot be avoided if a PCM.CODEC currently on the market is merely combined with a DSP.
In order to solve the above problem of S/N deterioration, consideration is given to use of a quantization apparatus with a smaller quantizing step than an 8-bit quantizing apparatus, which can maintain the same step size up to a high level, as a converter corresponding to A/D converter 8 and D/A converter 70 in FIG. 2. For example, use of a linear converter performing 16 bit linear quantization may be considered. A linear converter for about 15 bits may be sufficient, depending on the degree of signal processing performed by the DSP but, considering that PCM.CODEC based on the 8 bit .mu.-law companding has a resolution which is similar to that of a 14-bit linear converter, a resolution of about 16 bits may be necessary.
Either an A/D or D/A converter having high resolution such as 15 or 16 bits has a more complicated circuit and a larger scale than PCM.CODECs currently on the market. Therefore 16 or 15 bit A/D or D/A converters are extremely disadvantageous in terms of cost. Further, a PCM.CODEC is installed with a low-pass filter and the above-recited linear converter with a high resolution does not have such filter. Thus, it has to be provided with a new low pass filter, causing a great cost increase and increasing the chip area.
In another example a digital PCM channel apparatus is constructed by combining the A/D and D/A converter with the DSP, a technology considered to enable a DSP to perform processing similar to the aforerecited equalizer, attenuator and balancing network, as explained below.
A general structure considered as a digital PCM channel apparatus based on the above structure will again be shown in FIG. 3. Here, hybrid transformer 21, A/D converter 23 and D/A converter 24 perform the same functions as those represented by the reference numbers 3, 8 and 10, respectively, in FIG. 2. The impedance of hybrid transformer 21 can be maintained constant, as in FIG. 2. Two-wire subscriber 20 and 4-wire transmission path 30 are also similar to those represented by the reference numbers 2 and 9 in FIG. 2. Preprocessing circuit 22 is shown by including amplifier 5, coarse attenuator 17 and LPF 7 in FIG. 2. Post-processing circuit 25 is represented by combining LPF 11, coarse attenuator 18 and amplifier 14 of FIG. 2. Although it is abbreviated in FIG. 2, it sometimes performs the process of emphasizing a high frequency component of an analog signal in order to raise the quality of a communication signal. In contrast, post-processing circuit 25, in some cases, performs a process in which characteristics of signals emphasized on the transmitting side return to the appropriate process.
In FIG. 3, input signal SIN converted to digital data by A/D converter 23 and receiving PCM signal RIN from 4-wire transmission path 30, is input to DSP 19. In DSP 19, transmission level setting equalizer 27 and receiving level setting equalizer 28 are realized as firmware and perform the same operation as equalizers 4 and 13, and attenuators 6 and 12 in FIG. 1. Namely, with regard to the above input signal SIN and receiving PCM signal RIM, a loss of frequency characteristics of signals on 2-wire subscriber line 20 or 4-wire transmission path 30 is accurately corrected within a telephone band, and a loss of signal level caused by a line is accurately corrected.
At this time a part of a signal advanced from post-processing circuit 25 to subscriber line 20, is turned to input DSP 19 through hybrid transformer 21 such that it is included in input signal SIN making it necessary for the component entered into DSP 19 to be cancelled. Therefore, the above component is produced from receiving output signal ROUT in precise balance circuit 29, and this is added to input signal SIN at adder 26 (actually, this is substraction) thereby cancelling the above component.
This process is performed to obtain a difference between received output signal ROUT i.e. a receiving system signal, and input signal SIN i.e. a transmitting system signal, and to bridge a receiving system and a transmitting system.
A digital transmission system including the digital PCM channel apparatus of FIG. 3 has a transmission speed of, for example, 64 Kbit/sec and operates in synchronization with an 8 KHz clock. As far as it is not a complete dependent synchronization network, in FIG. 3 a receiving system circuit such as D/A converter 24 operates in synchronization with a receiving clock extracted from received PCM signal RIN and a transmitting system circuit such as A/D converter 23 operates in synchronization with a transmitting clock produced within a channel apparatus not shown. In this case, a receiving clock is obtained by dividing a master clock of the other terminal station, and a transmitting clock is formed by dividing a master clock of the own station. Therefore, both transmitting and receiving clocks have an indicated frequency of 8 KHz but, as they do not use the same master clock, their frequencies are slightly different in practice, and this difference is around 10.sup.-4 at the maximum.
The difference of 10.sup.-4 means that, when transmitting system data is input 10000 times, the receiving system data becomes 10001.
This results in sampling timings of received PCM signal RIN and input signal SIN, which are input to DSP 19, always differing slightly. Therefore, even if a receiving signal component included in input signal SIN is intended to be cancelled by an output from precise balance circuit 29 to which a receiving PCM signal RIN is input into adder 26, the signals at different times are subjected to the addition and thus, the desired result is not obtained.
Moreover, when the difference is 10.sup.-4 at 8 KHz clock, data out running phenomenon occur at a rate of 1 timing per 1.25 seconds. Thus, the data at the time is lost.
Therefore, it is necessary to match one clock with the other clock. In this case, receiving PCM signal RIN is a signal which has already been sampled on the transmitting side and the receiving clock thereof already exists on the transmitting side. In order to receive received PCM signal RIN, the receiving clock is needed. Thus, the receiving clock is used as a transmitting clock.
Received PCM signal RIN comes from a transmitting terminal station through a plurality of repeater or relay stations. Thus, some jitter is added to the receiving PCM signal RIN through respective stations. Therefore, received PCM signal RIN already includes large jitter. Thus, if it is used as a transmitting clock it is transmitted through many relays before it reaches the other terminal station. Thereby, the amount of jitter is increased , greatly deteriorating the communication quality. Therefore, when a clock generator is provided in both terminal stations and is intended to maintain the same communication quality, as in the case where these clock generators are designed to synchronize accurately with each other, the distance which causes jitter becomes the distance of going and returning, or twice the one-way distance. Therefore, the relay distance is limited to 1/2 the ordinary relay distance.
An echo canceler cancels echo signals included in transmitted signals, the echo signals being formed by signals advancing to a subscriber through hybrid transformer 21 being turned back. The echo canceler produces suitable replica echo signals, based on received signals, and subtracts them from the signal being transmitted. This performs a process of bridging a transmitted signal and a received signal, thereby causing a problem similar to the above case.
To solve the above problems, a digital-signal clock-changing method is necessary. In this method, a digital PCM channel apparatus as shown in FIG. 3 operates a D/A converter 24, an A/D converter 23 and a precise balance circuit 29, in synchronization with a receiving clock. This enables a transmitting signal obtained from these signals to again be synchronized with a transmitting clock generated by the clock generator of the own station. The transmitting signal is thereby produced as output signal SOUT.
In this case, it is preferable to achieve good communication quality and to be able to miniaturize the apparatus.
FIG. 4 shows a block diagram of a conventional clock changing method. In FIG. 4, the first clock system digital data 34 are converted to analog data by a D/A converter 31 which operates in accordance with the first clock 35. Then, after the analog data is converted to data which is continuous with time, through analog low pass filter 32, the output from low pass filter 32 is converted to the second clock system digital data 37 by an A/D converter 33 which operates at the second clock 36, thereby achieving a clock changing.
However, in the apparatus shown in FIG. 4, input digital data is reconverted to analog data by D/A converter 31 and the analog data is again converted to digital data by A/D converter 33. Thus results in a production of a quantizing noise and deterioration of the communication quality. A further problem is that the apparatus shown in FIG. 4 needs an analog low pass filter 32 which, unlike a digital circuit, cannot be miniaturized even if it is integrated.